Sample	Top over-represented sequence
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_An1AmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_C24AmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_ColAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_CviAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_EriAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_KyoAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_LerAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n01_daplib_ShaAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n01_undetermined	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_An1AmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_C24AmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_ColAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_CviAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_EriAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_KyoAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_LerAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHm-input_aj8	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj1	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj2	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj3	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj4	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj5	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj6	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj7	0.0
HYN72DRX3_l01_n02_daplib_ShaAmpPoolHmB-input_aj8	0.0
HYN72DRX3_l01_n02_undetermined	1.3225594167948158